Most modern embedded processors employ variable length instruction encoding of their instructions sets to achieve a compact code size. Two approaches have been followed, depending on the existence of a legacy processor.
For a newly-designed instruction set, where code size is considered an important design criterion, mixed size encoding may be utilized. In this case, short and long instructions share the same encoding space. As a result, a mode switch is not necessary for decoding and executing different size instructions.
For instruction sets utilized before code size reduction was undertaken, the encoding space may already be too crowded to permit new op codes. Rather than redesigning the instruction set from scratch, usually a new mode of operation is created in which the processor decodes and executes newly-introduced instructions.
For the second case, before the processor can decode and execute the new instruction types, the processor needs to be put in the new mode. Usually this mode change from legacy mode to the new mode is achieved by setting or resetting a mode bit in a designated configuration register. This approach has shortcomings. The mode bit must be set before the processor starts decoding and executing the new instructions. An instruction in legacy mode must set the bit to switch to the new mode, and vice versa. This implies that if any of the legacy code modules are reused, they must be modified to effect this change of mode. This can have practical limitations, for example, when using precompiled library modules. The mode bit also implies certain overhead in terms of code size as well as cycles required to execute the added mode change instructions. In addition, every time the mode is changed, a pipelined processor must allow the pipeline to drain before it starts decoding instructions from a different mode. This may impact performance if the mode is switched frequently.
Accordingly, there is a need for improved methods and apparatus for variable length instruction encoding in legacy processors.